This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-186988, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a method of manufacturing a semiconductor device including a MISFET formed by burying a gate electrode in a trench.
In recent years, strong demand has arisen for increasing the integration degree and speed of semiconductor devices. To meet this demand, the size between elements and element size have been reduced to attain shrink in feature sizes while reduction of resistance of internal interconnection materials and reduction of parasitic capacitance have been examined.
Especially, a great challenge for a gate electrode having a conspicuous RC delay is to attain a low resistance. Recently, to reduce the resistance of a gate electrode, a polycide gate having a two-layered structure comprised of a polysilicon film and metal silicide film is widely employed. A refractory metal silicide film has a resistance lower than that of a polysilicon film by about one order of magnitude and therefore is a promising low-resistance interconnection material. As a silicide, tungsten silicide (WSix) has been most widely used for a long time.
However, to cope with a thin interconnection having a size of 0.15 xcexcm or less, the interconnection resistance need be further reduced to shorten the delay time. To realize a gate electrode having a low resistance corresponding to a sheet resistance of 1 xcexa9/xe2x96xa1 or less using tungsten silicide, the film thickness of the silicide layer must be increased. This makes it difficult to fabricate the gate electrode pattern or form an interlevel insulating film on the electrode. To avoid this, it is required to achieve a low sheet resistance without increasing the aspect ratio of the electrode.
Under these circumstances, a so-called metal gate structure in which a metal film is directly stacked on a gate insulating film without interposing a polysilicon film is promising. However, unlike the conventional gate electrode, this structure has disadvantages such as difficulty in gate electrode fabrication and poor heat resistance.
To avoid the above-described problems, a trench-buried-type gate electrode forming method has been proposed. More specifically, after a disposable gate electrode pattern is formed, a diffusion layer is formed via the disposable gate. Then, a gate sidewall insulating film and interlevel insulating film are formed around the disposable gate. The disposable gate is peeled to form a trench, and a metal material for forming a gate electrode is buried in this trench. When this technique is used, the annealing temperature after metal gate electrode formation can be made low.
However, when a gate insulating film is formed by deposition, the insulating film is deposited not only on the bottom surface of the trench but also on the side surface. Especially, when a high-dielectric constant film is used as a gate insulating film, the high-dielectric constant material is also deposited on the gate sidewall.
The insulating film on the gate electrode sidewall is reflected not only in the interconnection capacitance between the gate electrode and an adjacent interconnection but also in the capacitances between the gate electrode and the contact for connecting the source/drain region to an upper interconnection and between the source or drain and the gate electrode. That is, when an insulating film with high dielectric constant is used on the gate electrode sidewall, the parasitic capacitance of the interconnection increases to reduce the operation speed of the circuit.
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which an insulating film having a dielectric constant lower than that of the gate electrode is self-aligned to the sidewall of the gate electrode of a MISFET having a buried gate electrode to reduce the parasitic capacitance and suppress a decrease in circuit operation speed.
In order to achieve the above object, the present invention has the following arrangements.
According to the present invention, there is provided a semiconductor device comprising a source and drain formed in a semiconductor substrate, a crystallized gate insulating film formed on the semiconductor substrate in a region between the source and drain, a gate electrode formed on the gate insulating film, and an insulating film formed on a side surface of the gate electrode and having an amorphous structure formed from the same material as that of the gate insulating film.
The gate insulating film and the insulating film are preferably formed from a material selected from the group consisting of cerium oxide (CeO2), zirconium oxide (ZrO2), hafnium oxide (HfO2), thorium oxide (ThO2), yttrium oxide (Y2O3), calcium fluoride (CaF2), tin-calcium fluoride (CaSnF2), titanium-barium oxide (BaTiO3), and La2O3.
According to the present invention, there is also provided a method of manufacturing a semiconductor device, comprising the steps of forming a disposable gate on a semiconductor substrate in a region where a gate electrode is to be formed, forming a sidewall spacer on a sidewall of the disposable gate, forming a source and drain in the semiconductor substrate using the disposable gate and the sidewall spacer as a mask, forming an interlevel insulating film on the semiconductor substrate so as to cover the disposable gate, planarizing an upper surface of the interlevel insulating film to expose upper surfaces of the disposable gate and the sidewall spacer, removing the disposable gate to form a trench portion having a side surface formed from the sidewall spacer and a bottom surface formed from the semiconductor substrate, depositing a gate insulating film on the semiconductor substrate so as to cover the bottom surface and side surface of the trench portion, forming a gate electrode buried in the trench portion, and removing the sidewall spacer and the gate insulating film on the sidewall of the gate electrode.
(a) A low-dielectric constant insulating film having a dielectric constant lower than that of a thermal oxide film of silicon is preferably buried in a trench formed by removing the sidewall spacer and the gate insulating film.
(b) The low-dielectric constant insulating film is preferably formed from a material selected from the group consisting of SiO2, SiOF, Fluorinated Amorphous Carbon, Parylene F, Parylene N, Polynaphthalene, Hydrogen Silsesquioxane, Spin-On-Glass, Aerogel/Xerogel, Fluorinated Polyimide, Teflon, Benzocycrobutene, Polyaryl Ether, Fluorinated Polyaryl Ether, and Air gap.
According to the present invention, there is also provided a method of manufacturing a semiconductor device, comprising the steps of forming a disposable gate on a semiconductor substrate in a region where a gate electrode is to be formed, forming a sidewall spacer on a sidewall of the disposable gate, forming a source and drain in the semiconductor substrate using the disposable gate and the sidewall spacer as a mask, forming an interlevel insulating film on the semiconductor substrate so as to cover the disposable gate, planarizing an upper surface of the interlevel insulating film to expose upper surfaces of the disposable gate and the sidewall spacer, removing the disposable gate to form a trench portion having a side surface formed from the sidewall spacer and a bottom surface formed from the semiconductor substrate, depositing an insulating film having an amorphous structure on the semiconductor substrate so as to cover the semiconductor substrate on the bottom surface of the trench portion, epitaxially growing an insulating film having a single-crystal structure from the insulating film having the amorphous structure on the bottom surface of the trench portion to form a gate insulating film on the bottom surface of the trench, depositing a gate electrode material on the semiconductor substrate so as to bury the trench portion, and removing the gate electrode material on the interlevel insulating film and the insulating film having the amorphous structure to form a gate electrode buried in the trench portion.
(a) Before deposition of the gate electrode material, the insulating film having the amorphous structure on the side surface of the trench portion is preferably removed by etching.
(b) Before deposition of the gate electrode material, the insulating film having the amorphous structure on the side surface of the trench portion is preferably modified to form a conductor.
(b1) The insulating film is formed from an HfO2 film, and the insulating film is nitrided to form HfN as the conductor.
The present invention with the above arrangements has the following functions and effects.
Since no high-dielectric constant gate insulating film is formed on the sidewall of the gate electrode, the parasitic capacitance between the gate electrode and the source/drain can be decreased to increase the operation speed of the circuit.
When a low-dielectric constant film having a dielectric constant lower than that of the thermal oxide film of silicon is buried in the trench formed by removing the gate insulating film from the gate electrode sidewall, the parasitic capacitance between the gate electrode and the source/drain can be further decreased to increase the operation speed of the circuit.
When the insulating film having the amorphous structure is removed, the parasitic capacitance between the gate electrode and the source/drain can be further decreased to increase the operation speed of the circuit.
When the insulating film having the amorphous structure is modified into a conductor before deposition of the gate electrode material, the parasitic capacitance between the gate electrode and the source/drain can be further decreased to increase the operation speed of the circuit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.